Reference is made to FIG. 1 showing a circuit diagram for a voltage doubler circuit 100. The circuit 100 includes an n-channel MOS transistor MN1 having a source terminal coupled to node A and a drain terminal coupled to node NA1 and an n-channel MOS transistor MN2 having a source terminal coupled to node A and a drain terminal coupled to node NA2. The transistors MN1 and MN2 are cross-coupled with the gate terminal of transistor MN1 coupled to the drain terminal of transistor MN2 at node NA2 and the gate terminal of transistor MN2 coupled to the drain terminal of transistor MN1 at node NA1.
The circuit 100 further includes an n-channel MOS transistor MN3 having a source terminal coupled to node NA1 and a drain terminal coupled to node NB1 and an n-channel MOS transistor MN4 having a source terminal coupled to node NA2 and a drain terminal coupled to node NB2. The transistors MN3 and MN4 are cross-coupled with the gate terminal of transistor MN3 coupled to the source terminal of transistor MN4 at node NA2 and the gate terminal of transistor MN4 coupled to the source terminal of transistor MN3 at node NA1.
The circuit 100 still further includes an n-channel MOS transistor MN5 having a drain terminal coupled to node B and a source terminal coupled to node NA1 and an n-channel MOS transistor MN6 having a drain terminal coupled to node B and a source terminal coupled to node NA2. The gate terminal of transistor MN5 is coupled to node NB1 and the gate terminal of transistor MN6 is coupled to node NB2.
A capacitor C1 has one terminal coupled to node NA1 and another terminal coupled to receive a clock signal CK. A capacitor C2 has one terminal coupled to node NA2 and another terminal coupled to receive a clock signal CKN (which is a logical inversion of the clock signal CK). A bootstrap capacitor Cbs1 has one terminal coupled to node NB1 and another terminal coupled to receive a clock signal CKH. A bootstrap capacitor Cbs2 has one terminal coupled to node NB2 and another terminal coupled to receive a clock signal CKHN (which is a logical inversion of the clock signal CKH).
The clock signals CKH and CKHN are generated from the clock signals CK and CKN using a clock voltage boosting circuit 110 shown in FIG. 2. The circuit 110 includes an n-channel MOS transistor 112 having a source terminal coupled to a positive supply voltage node VDD and a drain terminal coupled to node 114 and an n-channel MOS transistor 116 having a source terminal coupled to the VDD node and a drain terminal coupled to node 118. The transistors 112 and 116 are cross-coupled with the gate terminal of transistor 112 coupled to the drain terminal of transistor 116 at node 118 and the gate terminal of transistor 116 coupled to the drain terminal of transistor 112 at node 114.
A capacitor C1′ has one terminal coupled to node 114 and another terminal coupled to receive the clock signal CK. A capacitor C2′ has one terminal coupled to node 118 and another terminal coupled to receive the clock signal CKN.
A CMOS inverter 120 has an input coupled to the VDD node and an output generating the clock signal CKH. A source terminal of the p-channel MOS transistor in inverter 120 is coupled to the node 114 and a source terminal of the n-channel MOS transistor in inverter 120 is coupled to receive the clock signal CK.
A CMOS inverter 122 has an input coupled to the VDD node and an output generating the clock signal CKHN. A source terminal of the p-channel MOS transistor in inverter 122 is coupled to the node 118 and a source terminal of the n-channel MOS transistor in inverter 122 is coupled to receive the clock signal CKN.
The clock voltage boosting circuit 110 functions to level shift the clock signals CK and CKN to generate the clock signals CKH and CKHN. FIG. 3A shows the waveforms for the clock signals CK and CKN. FIG. 3B shows the waveforms for the clock signals CKH and CKHN. It will be noted that the clock voltage boosting circuit 110 functions to boost the high voltage level of the clock signals CKH and CKHN to 2*VDD, with the high voltage level of the clock signals CK and CKN being VDD. The clock signals CKH and CKHN have a same phase as the clock signals CK and CKN, respectively.
The voltage doubler circuit 100 of FIG. 1 is operable to generate either a positive voltage or a negative voltage. When the voltage doubler circuit 100 is to be used as a positive voltage doubler (i.e., operating in a high positive voltage mode), an input voltage such as the supply voltage VDD is connected to node A and an output voltage such as a high positive voltage of 2*VDD is generated at node B. Conversely, when the voltage doubler circuit 100 is to be used as a negative voltage doubler (i.e., operating in a high negative voltage mode), an input voltage such as the ground supply voltage GND is connected to node B and an output voltage such as a high negative voltage of −VDD is generated at node A.
The voltage doubler circuit 100 advantageously operates from just two clocks (CK/CKH and CKN/CKHN).
The voltage doubler circuit 100 operates as follows in the high positive voltage mode:
To begin, assume that no clock is present. In this situation, the nodes NA1 and NA2 will be charged to the VDD-Vt voltage level, where Vt is the threshold voltage of the n-channel MOS transistors MN1 and MN2. Now, assume the clock signal is applied. With the clock signal CK at the VDD voltage level and the clock signal CKN at the 0 (ground GND) voltage level, then the clock signal CKH is at the 2*VDD voltage level and the clock signal CKHN is at the 0 voltage level. In this configuration, the node NA1 will shift to the 2VDD-Vt voltage level and the node NA2 will shift to the VDD voltage level. Due to the cross coupling between transistors MN3 and MN4, the node NB1 will be charged to the 3*VDD voltage level and the node NB2 will be charged to the VDD voltage level. As the node NB1 is at the 3*VDD voltage level and the node NA1 is at the 2*VDD voltage level, the n-channel MOS transistor MN5 has sufficient Vgs (gate to source voltage) to pass the 2*VDD voltage from node NA1 to node B. In this way, a high positive voltage (higher than input supply voltage VDD) is generated and passed for output. So, during high positive voltage mode operation, the voltage VDD is applied at node A and the 2*VDD voltage is generated at node B. During the opposite phase of the clocks, the nodes NA1 and NA2 switch between the VDD voltage level and the 2*VDD voltage level. Similarly, the nodes NB1 and NB2 switch between the VDD voltage level and the 3*VDD voltage level.
The voltage doubler circuit 100 operates as follows in the high negative voltage mode:
With the ground reference voltage GND applied to node B, when the clock signal CKH transitions to the 2*VDD voltage level, the clock signal CK is simultaneously at the VDD voltage level, and the n-channel MOS transistor MN5 turns on and node NA1 is charged to the 0 (GND) voltage level. During the next clock cycle, the clock signal CKH switches from the 2*VDD voltage level to the 0 voltage level, with the clock signal CK changing state from the VDD voltage level to 0 voltage level, and the node NA1 accordingly transitions from the 0 voltage level to the −VDD voltage level. Also, the node NB1 discharges to the −VDD voltage level via the transistor MN3 and the switch off of the transistor MNS. In this way, the node NA1 also goes to the −VDD voltage level. Due to effect of the clock signals CKN and CKHN, the node NA2 is charged to the 0 (GND) voltage level via transistor MN6. As the NA2 is at the 0 voltage level, and the NA1 is at the −VDD voltage level, this configuration causes the transistor MN1 to turn on and pass the −VDD voltage level voltage to the node A. During this negative high voltage mode of operation, the nodes NA1 and NA2 switch between the 0 voltage level and the −VDD voltage level, and vice versa. Similarly, the nodes NB1 and NB2 switch between the VDD voltage level and the −VDD voltage level, and vice versa.
It will be noted that the foregoing voltage levels in the positive and negative operating modes are mentioned with the assumption of an ideal operating situation when there is no current load at the output and there is no charge loss.
Implementation of the circuit 100 as an integrated circuit utilizes three different isolated P-type wells (PWELLS) for the bulk (body) of the transistors. Those PWELLS include: a first PWELL associated with node A for the bulk of transistors MN1 and MN2; a second PWELL associated with node NA1 for the bulk of transistors MN3 and MN5; and a third PWELL associated with node NA2 for bulk of transistors MN4 and MN6. Those skilled in the art recognize that the provision of three different isolated PWELL structures will occupy a significant amount of integrated circuit area. Additionally, because of the local connection of the isolated bulk to the source terminals of the transistors, the bulk becomes capacitive due to associated capacitance on the source node (this being specifically a concern at nodes NA1 and NA2 due to the large capacitance provided by capacitors C1 and C2).
There is a need in the art to address the foregoing concerns.